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In Figure 6-55 , the DMA registers are written during cycles B2 to B5. The PCI address is written during cycle B2, and
the data values are written during cycle B3. Once the DMA control register is written (cycle B4), a DMA cycle is
initiated, as normal. When DP_START is asserted, the BAR_SELECT output remains at '111', similar to a Target
configuration cycle. The PCI cycle completes, with the data word being taken from the internal DMA control register.
Figure 6-55 shows the equivalent PCI read transfer. The data word is written into an internal DMA register. Also
shown is a second backend cycle (R0–R7) that reads the data word from the internal registers once the DMA cycle
completes.
cycle[7:0]
20
W0 W1 W2 W4 W5 W6
A0 A1A2 A3 0 1 2 3 4 5 6 7 R0 R1 R2 R3 R4 R5 R6 R7 R8
clk
framen
cben[3:0]
ad[31:0]
par
devseln
irdyn
trdyn
reqn
gntn
be_req
be_gnt
be_write
be_read
6
0
DATA
be_address[7:0]
50 54 58 5C
50 54 58 5C
60
mast_active
dp_start
dp_done
mem_data_in[31:0]
ADDR
4 CR
102
mem_data_out[31:0]
Figure 6-55 · Direct DMA Read from the PCI Bus
v4.0
ADDR
DATA TC CR
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